August 4, 2005 -- Last week, Cortina Systems announced its Barcelona chip, which aggregates 24 Gigabit Ethernet (GbE) ports to a SPI-4.2 or SPI-3 interface. Barcelona integrates 24 GbE MACs, a classification engine and policer for each port, and an aggregate shaper for the 24 ports. After classification, a queue manager buffers packets in an external 128MB FCRAM with ECC. The chip provides four priority queues per port and uses a combination of strict priority and deficit round robin to schedule traffic from its queues.